1. Field of the Invention
The invention relates to dummy patterns and a method for generating dummy patterns, and more particularly, to dummy patterns and a method for generating dummy patterns used in planarization process.
2. Description of the Prior Art
Along with an increase in speed of semiconductor devices, downsizing and higher integration of elements, such as transistors and multilevel interconnects are now in progress. An ever increasing accuracy and precision for forming circuit layout with higher density on the wafer is therefore required. Of course, those of ordinary skill in the art will easily recognize that layout with higher density requires better surface flatness of the wafer for increasing the accuracy for forming the layout pattern. Conventionally, chemical mechanical polishing (CMP) process is an effective and important method for wafer planarization. And result of CMP becomes critical for forming necessary elements. In detail, wafer regions with a low pattern density are known to be etched faster than wafer regions with high pattern density. Thus, for a given etch time, a disproportionately greater amount of material is etched from the low pattern density regions than the high pattern density regions. Accordingly, thickness in the low pattern density regions is smaller than that in the high pattern density regions, and thus an uneven surface having film thickness variation, dishing, or erosion is resulted. Besides the thickness variation problem, the uneven surface after CMP process further suffers serious problems such as pattern size error and poor critical size uniformity (CDU). Furthermore, it is found that different pattern densities also adversely impact other semiconductor process such as patterning process or etching process. For example, over-etching and/or incomplete etching may be resulted due to the different pattern densities on one wafer.
As a countermeasure against to the above problems, there have been proposed a method in which dummy patterns are randomly positioned in the low pattern density regions. By positioning the dummy patterns in the low pattern density regions, the pattern density is raised. Accordingly, the approach of inserting dummy patterns between design patterns is now essential for controlling variations in the flatness of the surface of a wafer or a chip.
However, the conventional approach uses dummy patterns with identical shape and size arranged in an array. Though the dummy patterns alleviate density difference between the low pattern density regions and the high pattern density regions, it is no longer competent when the wafer or the chip is formed to have more regions with varied densities due to the complexity of the integrated circuit (IC) design. Furthermore, the conventional dummy patterns also suffer from several drawbacks and limitations such as being irresistible to stress between regions with different pattern densities and increases optical proximity correction (OPC) processing time.
In view of the above, there exists a need for innovative dummy patterns and a smart method for generating dummy patterns.